Aside from our IEA Project, our research primarily focuses on two areas of design challenges:

1. To overcome the challenges in functional verification

2. To overcome the challenges in achieving design-manufacturing convergence

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Functional verification research includes:

• Automatic test bench improvement

• Mining and learning functional simulation data

• Coverage evaluation and coverage metric development

• Combined SAT, symbolic simulation, and data learning in verification

• Development of design drivers for the research

• Interface to existing constrained verification environment

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Design-manufacturing convergence research includes:

• Statistical timing tools and methodologies for test and diagnosis

• Test data learning

• Layout driven diagnosis and silicon debug

• Timed and statistical timed ATPG

• Information flow back from test data to design tools and models

• Monte Carlo simulation of combined timing effects

• Modeling and handling of design behavior variations